Recently, with advancement of automation of control, demands of safety and reliability for an electronic control device increase. To secure the safety of the electronic control device, it is required to detect abnormality and stop an operation immediately, when the abnormality occurs.
Conventionally, a logic circuit is often realized by an application specified integrated circuit (ASIC) based on a cell-based integrated circuit (CBIC) providing fixed logic or a gate array. Particularly, in a high reliable/high safe system, the logic circuit is generally realized by a device of the fixed logic. For example, in PTL 1, technology for realizing the high reliable/high safe system by a self check of a comparator is disclosed.
However, recently, with improvement of integration according to Moore's Law, a cost of designing and manufacturing a mask to manufacture the ASIC tends to increase and it is predicted that the ASIC cannot be applied unless products are not mass-produced. Particularly, in the high reliable/high safe system to be a target of the present invention, an amount of production is limited by the specialty of a use.
Therefore, a use of a programmable logic device (PLD) such as a field programmable gate array (FPGA) where an initial expense is suppressed at the time of manufacturing is expected. A feature of the programmable logic device is that the programmable logic device can be held in a memory (configuration memory: CRAM) capable of rewriting logic information and logic can be set at a user side later. Particularly, a high integrated FPGA mainly has a structure in which the memory is held by a static random access memory (SRAM). Hereinafter, such a type of programmable logic device is called an SRAM-based programmable logic device.